The present invention relates to a semiconductor memory having memory cells of MOS transistors and, more particularly, to a sense amplifier thereof.
A conventional sense amplifier in a CMOS semiconductor device has the structure shown in FIG. 1. Memory cells 11i1, 11i2, . . . , 11ij, . . . , and line are arranged in areas partitioned by word lines WL1, WL2, . . . , WLi, . . . , and WLn and bit lines BLi and BLi. Data (voltages V1 and V2 of the bit lines BLi and BLi) read out from one of the memory cells 11i1, 11i2, . . . , 11ij, . . . , and 11in is supplied to a first MOS differential amplifier 12 through the corresponding one of the word lines WL1, WL2, . . . , WLi, . . . , and WLn. The first differential amplifier 12 comprises: a pair of n-channel differential input MOS transistors Q4 and Q5 which have gate electrodes respectively connected to the bit lines BLi and BLi and which are arranged such that one end of the n-channel differential input MOS transistor Q4 is connected to one end of the n-channel differential input MOS transistor Q5; an n-channel MOS transistor Q1 inserted between a common node between the differential input MOS transistors Q4 and Q5 and a power supply V.sub.SS and having a gate electrode which receives a chip enable signal CE; an n-channel MOS transistor Q6 and a p-channel MOS transistor Q2 connected in series between the other end of the MOS transistor Q4 and a power supply V.sub.DD ; and an n-channel MOS transistor Q7 and a p-channel MOS transistor Q3 connected in series between the other end of the MOS transistor Q5 and the power supply V.sub.DD. The gate electrodes of the MOS transistors Q2 and Q3 are connected to the power supply V.sub.DD. An output CDi from a column decoder (not shown) is supplied to the gate electrodes of the MOS transistors Q6 and Q7. Voltages at a node N1 between the MOS transistors Q2 and Q6 and a node N2 between the MOS transistors Q3 and Q7 become outputs from the first differential amplifier 12. The output signals from the first differential amplifier 12 are supplied to a second MOS differential amplifier 13.
The second differential amplifier 13 comprises: a pair of differential input n-channel MOS transistors Q8 and Q9 which have gate electrodes respectively connected to the nodes N1 and N2 and each of which has one end connected to the power supply V.sub.SS ; and p-channel MOS transistors Q10 and Q11 which are respectively inserted between the other end of the MOS transistor Q8 and the power supply V.sub.DD and between the other end of the MOS transistor Q9 and the power supply V.sub.DD and which constitute a current mirror circuit. An output from the second differential amplifier 13 appears at a node N3 between the MOS transistors Q11 and Q9 and is supplied to an output buffer 14. The output buffer 14 comprises a CMOS inverter having a p-channel MOS transistor Q12 and an n-channel MOS transistor Q13. A sense output signal appears at a node between the MOS transistors Q12 and Q13.
The operation of the conventional sense amplifier having the configuration described above will be described. When the chip enable signal CE supplied to the n-channel MOS transistor Q1 goes high, the MOS transistor Q1 is turned on, so that sense operation is ready. When the output signal CDi from the column decoder goes high and the ith column is selected, the MOS transistors Q6 and Q7 are turned on. Data is read out onto the bit lines BLi and BLi from the memory cell 11ij (of the memory cells 11i1, 11i2, . . . , 11ij, . . . , and 11in connected to the bit lines BLi and BLi) which is selected by the word line WLj. Therefore, one of the bit lines BLi and BLi goes high in accordance with the content of the data read out from the memory cell 11ij, and the other goes low. In accordance with changes in voltages in the bit lines BLi and BLi, one of the MOS transistors Q4 and Q5 having gate electrodes respectively connected to the bit lines BLi and BLi is turned on, and the other is turned off. In accordance with the ON/OFF operation of the MOS transistors Q4 and Q5, voltages at the node N1 between the MOS transistors Q2 and Q6 and the node N2 between the MOS transistors Q3 and Q7 change. These voltages are applied to the gate electrodes of the differential input MOS transistors Q8 and Q9 of the second differential amplifier 13. A constant current is supplied to the MOS transistors Q8 and Q9 from the MOS transistors Q10 and Q11 which constitute the current mirror circuit. A voltage at the node N3 between the MOS transistors Q9 and Q11 changes in accordance with the ON/OFF operation of the MOS transistor Q9 and is applied to the signal input terminal of the output buffer 14. In the output buffer 14, one of the MOS transistors Q12 and Q13 is turned on and the other is turned off in accordance with the voltage at the node N3. As a result, an output signal corresponding to the data stored in the selected memory cell 11ij appears at the node between the MOS transistors Q12 and Q13.
In the readout operation with respect to the memory cells, a ratio (converted by the load MOS transistors Q2 and Q3 to a voltage) of a current flowing through the differential input MOS transistor Q4 to a current flowing through the differential input MOS transistor Q5 is given as follows: ##EQU1## where V1 and V2 are voltages on the bit lines BLi and BLi, respectively; .DELTA.V is the potential difference between the voltages V1 and V2; V0 is the source voltage of each of the MOS transistors Q4 and Q5; and Vth is the threshold voltage of each of the MOS transistors Q4 and Q5. The first differential amplifier 12 has the maximum sensitivity when V1-V0-Vth=0 is given. However, when the first differential amplifier 12 is arranged under this condition, a transconductance gm thereof is decreased, thus requiring a long period of time to drive the second differential amplifier 13 at the next stage. In order to increase the transconductance and provide a high sense sensitivity, a large potential difference .DELTA.V across the bit lines BLi and BLi must be set.
When a current flowing in the bit line is given as Ib, a transient time td from low level to high level and vice versa with respect to the bit line potential is given as follows: EQU td=Cb.multidot..DELTA.V/Ib (2)
where Cb is the bit line capacity. When the potential difference .DELTA.V is set large, the transient time td with respect to the bit line potential becomes large.
As described above, the sensitivity of the sense amplifier having a series circuit of two MOS differential amplifiers is inversely proportional to the transconductance gm thereof. It is difficult to simultaneously shorten signal delay times of the bit line and the sense circuit arrangement.